1. Field of the Invention
The present invention relates to a one-transistor (1T) floating-body DRAM cell device, and more particularly, to a 1T floating-body DRAM cell device of which performance can be improved by providing a double-gate structure having a non-volatile function to one electrode and by forming source and drain regions so as not to be in contact with an underlying gate stack.
2. Description of the Related Art
An existing dynamic random access memory (DRAM) cell is constructed with one metal oxide semiconductor (MOS) transistor and one cell capacitor. Recently, as a degree of integration in a DRAM is increasingly required, a size of a cell device needs to be reduced, and a size of a cell capacitor needs to be reduced. Such a miniaturization of the cell device and the cell capacitor in the MOS device requires very difficult manufacturing processes. Recently, MOS devices having a floating body have been used as DRAM cell devices. In the devices, DRAM memory operations may be performed by storing or removing charges in the floating body. In this technology, since one MOS cell device is used, the DRAM can be implemented by using simple processes unlike the conventional DRAM Such a DRAM cell device is referred to as a 1T floating body DRAM cell device (hereinafter, simply referred to as a “1T DRAM cell device” or a “1T-DRAM cell device”). In addition, the 1T DRAM cell device can be embedded in an existing logic circuit (for example, a micro-processor or a network-processor). In this case, the 1T DRAM cell device is called an eDRAM cell device. The 1T DRAM cell device used in the eDRAM has a high memory capacity or a high operating speed, so that its applications are increased. The 1T DRAM cell device has a floating body. The adjacent floating bodies are electrically isolated from each other so as to be floated. The 1T DRAM cell device includes a floating body. The floating body of the 1T DRAM cell device is electrically isolated from adjacent bodies so as to be floated. Therefore, information can be stored in the floating body. As a result, unlike an existing DRAM cell device, the 1T DRAM cell device does not require a cell capacitor, so that a cell area can be reduced. Accordingly, a degree of integration of the DRAM cell device can be improved.
FIGS. 1A and 1B are cross-sectional views illustrating 1T DRAM cell devices having a double-gate structure in the related art. The 1T DRAM cell device shown FIG. 1A is disclosed in U.S. Pat. No. 7,239,549. Referring to FIG. 1A, a first insulating layer 2 is formed on a semiconductor substrate 1, and a single-crystalline silicon layer is formed on the first insulating layer 2. The single-crystalline silicon layer includes a floating body 3 and a source 8 and a drain 9 that are formed at the left and right sides of the floating body 3. A gate insulating layer 10 is formed the single-crystalline silicon layer including the floating body 3, the source 8, and the drain 9, and a gate electrode 11 is disposed on the gate insulating layer 10.
Now, operations of the 1T DRAM cell device shown in FIG. 1A are described in brief. In the description hereinafter, the 1T DRAM cell device is assumed to be an NMOS cell device. The same description can be made in the case of a PMOS cell device. First, a “write 1” operation is described. In the “write 1” operation, the source 8 is grounded, and voltages are applied to the drain 9, that is, a bit line, and to the gate electrode 11, that is, a word line, so that impact ionization can easily occur. As a result, holes are generated in the floating body 3 in the vicinity of the drain 9. Some portions of the holes are accumulated, and others pass through a potential barrier to be flown to the source 8. A threshold voltage of the device is changed by a concentration of the hole accumulated in the floating body 3, so that a drain current is changed in a read operation. According to the “write 1” operation, excessive holes may exist in the floating body 3, and the threshold voltage of the device may be decreased, so that the drain current may be increased. Now, a read operation is described. In the read operation, a voltage that is the threshold voltage or more is applied to the gate electrode 11, and a bit line read voltage that is lower than that of the “write 1” operation is applied to the drain 9. There is a difference in the drain current according to whether the holes in the floating body 3 are in an excessive state or in a depleted state due to erasing. By reading the difference in the drain current, the information stored in the DRAM cell device can be recognized.
Finally, a “write 0” operation is described. In the “write 0” operation, an appropriate voltage is applied to the gate electrode 11, and a negative voltage is applied to the drain 9. As a result, the holes in the floating body 3 are leaked into the drain 9, so that the floating body 3 is in the hole depleted state. Accordingly, the threshold voltage of the device is increased.
Now, as another example of the “write 1” operation, a method using GIDL (gate induced drain leakage) is described. In this operation, a voltage of 0V or a negative voltage is applied to the gate electrode 11 of the device, and a positive voltage is applied to the drain 9 connected to the bit line. As a result, electron-hole pairs are generated in the area, where the drain 9 and the gate electrode 11 are overlapped, due to band-to-band tunneling. The electrons flow to the drain 9, and the holes are stored in the floating body 3.
In addition, as still another example of the “write 1” operation, a method using a bipolar effect (floating base bipolar action) is described. In this operation, a voltage of 0V or a low negative voltage is applied to the gate electrode 11 of the device, and a high positive voltage is applied to the drain 9 connected to the bit line. As a result, electron-hole pairs are generated due to avalanche breakdown between the drain 9 and the floating body 3. The electrons flow to the drain 9, and the holes are stored in the floating body 3.
The proceeding from the structure shown in FIG. 1A to the structure shown in FIG. 1B denotes a miniaturization of the length Lg of gate electrode. The miniaturization of the DRAM cell device is very important because it leads to an increase in capacity of the DRAM cell device. However, due to the miniaturization of channel length, a short channel effect occurs. In addition, a size of the floating body which stores information is reduced, so that a difference in drain current between the “write 1” state and the “write 0” state is decreased. Accordingly, it is difficult to sense and to store information for a long time.
In order to solve the problem, several 1T DRAM cell devices having a double-gate structure have been proposed. The double-gate structure is known to be effective in the miniaturization of device. Hereinafter, the representative structure among the proposed double-gate structures will be described in detail. Now, four representative structures among the proposed double-gate structures are described. FIGS. 2A to 2D are cross-sectional views illustrating existing 1T-DRAM cell devices having a double-gate structure. In these 1T-DRAM cell devices, basically, an upper gate electrode 11 and a substrate 1 are used, or an additional electrode is inserted as a lower electrode. In addition, in these 1T-DRAM cell devices, by using a bias of the lower electrode, the holes can be retained in the floating body 3 for a long time, and the sensing margin can be increased. The structures of the 1T-DRAM cell devices are described hereinafter.
FIG. 2A illustrates a structure of a 1T-DRAM cell device disclosed in an article, “A Capacitor-less Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications,” (IEEE Trans. on Electron devices, vol. 50, no. 12, pp. 2408-2416, 2003) by Charles Kuo et al. in UC Berkeley. In the example, an upper gate 11 and a lower gate 25 are disposed on and under a floating body 3, respectively. The upper gate 11 and the lower gate 25 are electrically independent of each other. In the 1T DRAM cell device, due to the characteristics of the double-gate structure, it is possible to suppress the short channel effect and to improve the sensing margin. In the 1T DRAM cell device, a negative voltage (for example, −1V) is applied to the lower gate 25, so that the holes can be retained in the floating body 3 in the “write 1” operation for a long time. In addition, during the erase operation, a voltage of 0V is applied to the lower gate 25, so that the holes in the floating body 3 can effectively flow into a drain. Accordingly, it is possible to improve the sensing margin. However, the 1T DRAM cell device has the problems as follows. Generally, in the case where the floating body 3 in the double-gate structure has a small thickness and is fully depleted, a width of the body is configured to be small due to its characteristics of suppressing the short channel effect. A threshold voltage in the double-gate structure having a fully-depleted body depends on the thickness of the body and a doping concentration of the body. Although a fully-depleted cell device can be actually manufactured, a variation in the threshold voltage among the cell devices may be greatly increased. Therefore, it is difficult to implement a practical cell device. In addition, since the lower gate electrode 25 are independently provided to each cell device, there is a problem in that a degree of integration of the cell devices is greatly decreased in a layout of a cell device array.
FIG. 2B illustrates another example of an existing 1T DRAM cell device having a double-gate structure disclosed in an article “Floating Body DRAM Characteristics of Silicon-On-ONO (SOONO) devices for System-on-Chip (SoC) Applications” (in VLSI Tech., Dig., 2007, pp. 168-169.) by Chang Woo Oh et al., of Samsung electronics. In the cell device, an existing bulk silicon substrate is used as a substitute for an SOI substrate, and an SiGe layer is used as a sacrificial layer so as to implement a floating body 3. In FIG. 2B, spaces filled with a fourth insulating layer 21 and a first nitride layer 22 are the regions where the SiGe layer initially exists. A thickness of the insulating layers is about 50 nm. In the cell device, in order to obtain the double-gate effect, the substrate 1 is used like a lower electrode. Although the sensing margin can be improved due to the double-gate effect, the 1T DRAM cell device has the problems as follows. Firstly, since a thickness (about 50 nm in this example) of the insulating layer formed between the substrate 1 and the floating body 3 is too large, a high voltage of about −5V needs to be always applied so as to store the generated holes in the floating body 3. The thickness of the insulating layer may be reduced by reducing a thickness of the sacrificial layer of the SiGe layer in the cell device manufacturing processes. However, if the thickness is reduced, much difficulty is involved with the processes. Secondly, in the case where the substrate 1 is used as a common lower gate electrode for all cell devices, so that it is impossible to apply a bias to only a specific cell device or to only cell devices within a specific area. In addition, if the lower gate electrodes 7 are formed, in order to localize each of the lower gate electrodes 7 to each of the cell devices, that is, in order to electrically independently form the lower gate electrodes, wells may be formed in the substrate 1. However, in this case, since an interval between the wells needs to be enlarged, a degree of integration is greatly decreased. Thirdly, as described in FIG. 2A, since the fully-depleted floating body needs to be used, there is an essential problem in that a dispersion of read currents among the cell devices is increased.
FIG. 2C illustrates still another example of a double-gate structure disclosed in an article “Scaling of Flash NVRAM to 10's of nm by Decoupling of Storage from Read/Sense Using Back-Floating Gates,” (IEEE Trans. on Nanotechnology, vol. 1, no. 4, pp. 247-254, December 2002) by Arvind Kumar et al, in Cornell University. The double-gate structure is contrived for applications of an existing flash memory other than a 1T DRAM cell device. According to the disclosed article, write and erase operations are performed by storing or removing charges in or from a floating storage node 24 through a bottom electrode 23, and a memory storage state is read by using an upper gate electrode 11. However, according to the disclosed article, a change in threshold voltage during the write and erase operations of the cell device is not good. Although this structure is contrived for a flash device, the structure may be adapted to a 1T DRAM cell device. However, there is not disclosed a 1T DRAM cell device using this structure. If the structure is directly adapted to the 1T DRAM cell device, there are problems as follows. Firstly, since a thickness of an insulating layer interposed between a floating body 3 and a bottom electrode 23 having an effect of a lower electrode is too large, a very high voltage needs to be applied to the bottom electrode 23 so as to obtain the double-gate effect. If a thickness of insulating layers on and under a floating storage node 24 is decreased so as to reduce the voltage, the cell device cannot be operated as an appropriate flash memory. In particular, since the floating storage node 24 in the disclosed structure is a conductive layer, a thickness of a tunneling insulating layer disposed thereon needs to be at least about 7 nm so as not to lose information. Secondly, since the bottom electrodes 23 formed in the substrate 1 are not electrically isolated between the cell devices, a lower electrode effect for a specific cell device or for a plurality of cell devices within a specific area cannot be reduced. In the disclosed document, in a method of forming the bottom electrode, a heavily-doped substrate or a substrate of which the upper portion is heavily doped is used. In other words, the bottom electrode 23 is formed by doping the substrate 1 with impurities. In this case, since an interval between the bottom electrodes 23 of the cell devices needs to be enlarged so as to electrically independently provide the bottom electrodes 23 to the cell devices, there is a problem in that a degree of integration in an array of the cell devices is greatly decreased. Thirdly, as described above with reference to FIGS. 2A and 2B, since the dispersion of the threshold voltages among the cell devices having fully-depleted floating body 3 is too large, it is difficult to practically implement the 1T DRAM cell device.
FIG. 2D illustrates an example of a double-gate structure having a non-volatile function disclosed in Korean Patent Application No. 10-2007-0086516 by Kyungpook National University. In the invention, a gate electrode 11 and a control electrode 7 are formed on and under a semiconductor layer where a source 8, a drain 9, and a floating body 3 are formed, so that a double-gate structure having an excellent miniaturization characteristic is implemented. The lower control electrode 7 is surrounded by a so-called gate stack. The gate stack is constructed with a tunneling insulating layer 4, a charge storage node 5, and a blocking insulating layer 6, and the control electrode 7 has the same function as a control electrode of an existing non-volatile memory device. In other words, according to a bias condition to the control electrode 7, write or erase operation can be performed on the charge storage node 5. In the case where a fully-depleted floating body is formed, if charges are stored through the control electrode 7 in the charge storage node 5, good miniaturization characteristic of the cell device can be obtained; a dispersion of the threshold voltage can be reduced by adjusting a charge amount of the charge storage node 5; a degree of integration of an array of cell devices can be improved by commonly using the control electrode 7; the performance of DRAM can be improved by adding a memory function to the write, erase, and read operations. However, since the source 8 and the drain 9 are formed so as to be in contact with the gate stack, there occur problems in the “write 0” characteristic and the retention characteristic. In order to describe the problems, an n-type FET device is assumed. Since the cell device is an n-type FET device, the regions of the source 8 and the drain 9 are doped with n+ type impurities. Since holes need to be accumulated in the lower portion of the floating body 3 in order to improve the performance of the cell device, negative charges need to be stored in the charge storage node 5 of the gate stack, or a negative voltage needs to be applied to the control electrode 7. Under the condition for accumulating the holes, large band bending occurs in the regions of the source 8 and the drain 9 which are overlapped with the gate stack, and due to band-to-band tunneling, electron-hole pairs are generated. The electrons flow into the drain 9, and the holes are stored in the floating body 3. As a result, there are problems in that the “write 0” characteristic and the retention characteristic deteriorate. Due to the problems, the length of the control electrode 7 and the length of the gate stack surrounding the control electrode 7 cannot be configured to be large. Accordingly, the capacitance of the floating body 3 is reduced, so that the sensing margin and the retention time characteristic deteriorate.